The Impact of Back Bias on The Random Telegraph Noise in the Co-intregrated Strained CMOS on Ultra-Thin Body and BOX SOI Platform

Xinze Li

doi:https://doi.org/10.7567/SSDM.2023.F-1-05

Presentation information

Oral Presentation

01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[F-1] Modeling, Simulation and Characterization

Wed. Sep 6, 2023 2:00 PM - 3:45 PM Room F (224, Bldg. 2)

Session Chairs: Satofumi Souma (Kobe Univ.), Hidetoshi Oishi (Sony Semiconductor Solutions Corp.)

3:00 PM - 3:15 PM

[F-1-05] The Impact of Back Bias on The Random Telegraph Noise in the Co-intregrated Strained CMOS on Ultra-Thin Body and BOX SOI Platform

^○Xinze Li¹, Sebastien Loubriat², Guillaume Besnard³, Christophe Maleville³, Olivier Weber⁴, Ran Cheng¹ (1. Zhejiang Univ. (China), 2. CEA-LETI Corp. (France), 3. SOITEC Corp. (France), 4. STMicroelectronics Corp. (France))

https://doi.org/10.7567/SSDM.2023.F-1-05

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Presentation information

[F-1] Modeling, Simulation and Characterization

[F-1-05] The Impact of Back Bias on The Random Telegraph Noise in the Co-intregrated Strained CMOS on Ultra-Thin Body and BOX SOI Platform

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