IGZO Capacitorless DRAM shows a great prospect in next generation DRAM technology due to long retention time and BEOL capability for stacking up, but still faces the challenges in high-density scaling limit of area per bit-cell and random read error when integrating large array. Here, towards high-density application, we demonstrate vertical Channel-all-around IGZO FETs based DRAM with 4F² bit-cell area and long retention time over 300 seconds. Towards reliable read operation, we demonstrate ultra-scaled dual-gate IGZO FETs based DRAM by using one gate to control read and another for storage, achieving reliable gate-controlled read scheme with efficient electrical performance.