Highly Error-tolerant Low Power CiM by Co-design of SLC Mask & MLC Weight Twin FeFETs and Strong Lottery Ticket Hypothesis Neural Network Algorithm

Kenshin Yamauchi

doi:https://doi.org/10.7567/SSDM.2023.K-6-02

Presentation information

Oral Presentation

02: Advanced and Emerging Memories / New Applications

[K-6] In-Memory and Unconventional Computing 1

Fri. Sep 8, 2023 10:45 AM - 12:00 PM Room K (234, Bldg. 2)

Session Chairs: Wein-Town Sun (eMemory Technology Inc.), Ming-Hsiu Lee (Macronix International Co., Ltd)

11:00 AM - 11:15 AM

[K-6-02] Highly Error-tolerant Low Power CiM by Co-design of SLC Mask & MLC Weight Twin FeFETs and Strong Lottery Ticket Hypothesis Neural Network Algorithm

^○Kenshin Yamauchi¹, Ayumu Yamada¹, Naoko Misawa¹, Seong-Kun Cho¹, Kasidit Toprasertpong¹, Shinichi Takagi¹, Chihiro Matsui¹, Ken Takeuchi¹ (1. Univ. of Tokyo (Japan))

https://doi.org/10.7567/SSDM.2023.K-6-02

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Presentation information

[K-6] In-Memory and Unconventional Computing 1

[K-6-02] Highly Error-tolerant Low Power CiM by Co-design of SLC Mask & MLC Weight Twin FeFETs and Strong Lottery Ticket Hypothesis Neural Network Algorithm

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