Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs

Yannik Junk

doi:https://doi.org/10.7567/SSDM.2023.PS-1-13

[PS-1-13] Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs

Yannik Junk¹, Omar Concepción Diaz¹, Marvin Frauenrath^2,3, Florian Bärwolf⁴, Andreas Mai⁴, Jean-Michel Hartmann^2,3, Detlev Grützmacher¹, Dan Buca¹, ^○Qing-Tai Zhao¹ (1. Peter-Grünberg-Institut (PGI-9) and JARA-FIT, Forschungszentrum Jülich (Germany), 2. CEA-LETI, MINATEC Campus, F-38054 Grenoble (France), 3. Univ. of Grenoble Alps (France), 4. IHP-Leibniz-Institut für innovative Mikroelektronik, 15236 Frankfurt (Oder) (Germany))

https://doi.org/10.7567/SSDM.2023.PS-1-13

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講演情報

[PS-1] 01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[PS-1-13] Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs

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