Investigation of Top-gate MoS<sub>2</sub> FETs by Low-temperature ALD High-κ and Hydrazine Passivated Interface

Min- Kun Huang

doi:https://doi.org/10.7567/SSDM.2023.PS-8-12

[PS-8-12] Investigation of Top-gate MoS₂ FETs by Low-temperature ALD High-κ and Hydrazine Passivated Interface

^○Min- Kun Huang¹, Hsu-Tang Liao², William Cheng-Yu Ma², Yeong-Her Wang¹, Chun-Jung Su^3,4 (1. National Cheng Kung Univ. (Taiwan), 2. National Sun Yat-sen Univ. (Taiwan), 3. National Yang Ming Chiao Tung Univ. (Taiwan), 4. Taiwan Semiconductor Research Inst. (Taiwan))

https://doi.org/10.7567/SSDM.2023.PS-8-12

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Presentation information

[PS-8] 08: Low Dimensional Devices and Materials

[PS-8-12] Investigation of Top-gate MoS₂ FETs by Low-temperature ALD High-κ and Hydrazine Passivated Interface

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Presentation information

[PS-8] 08: Low Dimensional Devices and Materials

[PS-8-12] Investigation of Top-gate MoS2 FETs by Low-temperature ALD High-κ and Hydrazine Passivated Interface

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[PS-8-12] Investigation of Top-gate MoS₂ FETs by Low-temperature ALD High-κ and Hydrazine Passivated Interface