Analysis of Horizontal-Mura Caused by Reset’s Abnormal Delay of GOA Output

Xinmao Qiu

doi:https://doi.org/10.36463/idw.2019.0612

2:30 PM - 5:00 PM

[AMDp2-11] Analysis of Horizontal-Mura Caused by Reset’s Abnormal Delay of GOA Output

*Xinmao Qiu¹, Yao Liu¹, Hongjiang Wu¹, Hongtao Lin¹, Baoqiang Wang¹, Wenchao Wang¹, Yaochao Lv¹, Guichun Hong¹, Min Zhou¹, Zuwen Liu¹ (1. Fuzhou BOE Optoelectronics Technology Co., Ltd (China))

Gate Driver on Array, Horizontal-Mura, Leakage Current, Array Design

https://doi.org/10.36463/idw.2019.0612

A rare failure named Horizontal-Mura Caused by Reset’s abnormal Delay of GOA Output is studied systemically. By increasing frame frequency, changing TFT size ratio and increasing channel Length, the leakage current of voltage Gout’s Gate (PU) can be reduced, and Mura phenomenon can be significantly alleviated.

Proceedings of the International Display Workshops Volume 26 (IDW '19)

[AMDp2-11] Analysis of Horizontal-Mura Caused by Reset’s Abnormal Delay of GOA Output