Highly Stable Dual Gate a-InGaZnO Thin Film Transistor with Top Gate to Drain Offset for AC Gate Pulse Stress

Sunaina Priyadarshi

doi:https://doi.org/10.36463/idw.2023.1049

4:40 PM - 5:00 PM

[DES2-1] Highly Stable Dual Gate a-InGaZnO Thin Film Transistor with Top Gate to Drain Offset for AC Gate Pulse Stress

*Sunaina Priyadarshi¹, Abidur Rahaman¹, Sabiqun Nahar¹, Jin Jang¹ (1. Kyung Hee University (Korea))

a-IGZO, TFT, dual gate, AC stress, drain offset

https://doi.org/10.36463/idw.2023.1049

The AC gate pulse stress has been performed on the top gate to drain offset (L_TG(Off)) dual gate (DG) a-IGZO TFT. It showed less threshold voltage-shift compared with the conventional DG TFT under pulse voltage stress of 0V to +30V at rising/falling time of 1- and 0.1-µs for 86.6 ks.

Proceedings of the International Display Workshops Volume 30 (IDW '23)

[DES2-1] Highly Stable Dual Gate a-InGaZnO Thin Film Transistor with Top Gate to Drain Offset for AC Gate Pulse Stress