[S-D-9] Two Mechanisms for Interface State Generation in n-MOSFETs

Naoki YASUDA, Kenji TANIGUCHI, Chihiro HAMAGUCHI (1.Department of Electronic Engineering, Osaka University, 2.Semiconductor Device Engineering Lab., Toshiba, Corporation)

https://doi.org/10.7567/SSDM.1989.S-D-9