[B-1-4] Optimization of Giga-bit DRAM Cell Transistors by Channel and Drain Engineering

M. Kojima、H. Suzuki、T. Miyashita、H. Anzai、T. Nagata、K. Takahashi、M. Sato、Y. Nara (1.Fujitsu Laboratories Ltd.)

https://doi.org/10.7567/SSDM.1998.B-1-4