Electroplating Cu Filling Study for Thorough Electrode in Silicon Wafer of Three Dimensional LSI Chip Stacking

M. Tomisaka; H. Yonemura; M. Hoshino; K. Takahashi

doi:https://doi.org/10.7567/SSDM.2001.B-1-3

[B-1-3] Electroplating Cu Filling Study for Thorough Electrode in Silicon Wafer of Three Dimensional LSI Chip Stacking

M. Tomisaka、H. Yonemura、M. Hoshino、K. Takahashi (1.Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET))

https://doi.org/10.7567/SSDM.2001.B-1-3

2001 International Conference on Solid State Devices and Materials

[B-1-3] Electroplating Cu Filling Study for Thorough Electrode in Silicon Wafer of Three Dimensional LSI Chip Stacking