A Highly Reliable 0.18 μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide

S. Maeda; K. Shiga; H. Naruoka; N. Hattori; T. Iwamatsu; T. Matsumoto; Y. Hirano; Y. Yamaguchi; T. Ipposhi; S. Maegawa; M. Inuishi

doi:https://doi.org/10.7567/SSDM.2001.C-6-3

[C-6-3] A Highly Reliable 0.18 μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide

S. Maeda、K. Shiga、H. Naruoka、N. Hattori、T. Iwamatsu、T. Matsumoto、Y. Hirano、Y. Yamaguchi、T. Ipposhi、S. Maegawa、M. Inuishi (1.ULSI Development Center, Mitsubishi Electric Corporation)

https://doi.org/10.7567/SSDM.2001.C-6-3

2001 International Conference on Solid State Devices and Materials

[C-6-3] A Highly Reliable 0.18 μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide