[A-2-4] Comparison of the Interconnect Capacitances of Various SRAM Cell Layouts To Achieve High Speed, Low Power SRAM Cells

Y. Tsukamoto, K. Nii, Y. Yamagami, T. Yoshizawa, S. Imaoka, T. Suzuki, A. Shibayama, H. Makino (1.LSI Product Technology Unit , Renesas Technology Corp., 2.Corporate Development Div., Semiconductor Company, Matsushita Electric Industrial Corp., 3.Electronic Devices Design Center, Renesas Device Design Corp.)

https://doi.org/10.7567/SSDM.2003.A-2-4