A Hierarchical 512-Kbit SRAM with 8 Read/Write Ports in 130nm CMOS

Seiji Fukae; Nobuhiko Omori; Tetsushi Koide; Hans Jurgen Mattausch; Tetsuo Hironaka

doi:https://doi.org/10.7567/SSDM.2003.G-1-4

2003 International Conference on Solid State Devices and Materials

Sep 16, 2003 - Sep 18, 2003
Keio Plaza Inter-Continental Tokyo (Keio Plaza Hotel), Tokyo, Japan

[G-1-4] A Hierarchical 512-Kbit SRAM with 8 Read/Write Ports in 130nm CMOS

Seiji Fukae, Nobuhiko Omori, Tetsushi Koide, Hans Jurgen Mattausch, Tetsuo Hironaka (1.Research Center for Nanodevices and Systems, Hiroshima University, 2.Department of Computer Engineering, Hiroshima City University)

https://doi.org/10.7567/SSDM.2003.G-1-4

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