Novel ESD Protection Design for Nanoscale CMOS Integrated Circuits

Ming-Dou Ker; Tang-Kui Tseng

doi:https://doi.org/10.7567/SSDM.2003.P2-8

2003 International Conference on Solid State Devices and Materials

2003年9月16日〜 2003年9月18日
Keio Plaza Inter-Continental Tokyo (Keio Plaza Hotel), Tokyo, Japan

[P2-8] Novel ESD Protection Design for Nanoscale CMOS Integrated Circuits

Ming-Dou Ker、Tang-Kui Tseng (1.Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics National Chiao-Tung University、2.ESD Protection Technology Department, System-on-Chip Technology Center Industrial Technology Research Institute)

https://doi.org/10.7567/SSDM.2003.P2-8

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