Investigation of Degradation model for Ultra -thin Gate Dielectrics

Hiroko Mori; Hideo Ehara; Naoyoshi Tamura; Chioko Kaneta; Hideya Matsuyama; Ken Shono

doi:https://doi.org/10.7567/SSDM.2004.A-7-1

2004 International Conference on Solid State Devices and Materials

Sep 14, 2004 - Sep 17, 2004
Tower Hall Funabori, Tokyo, Japan

[A-7-1] Investigation of Degradation model for Ultra -thin Gate Dielectrics

Hiroko Mori, Hideo Ehara, Naoyoshi Tamura, Chioko Kaneta, Hideya Matsuyama, Ken Shono (1.FUJITSU LSI Quality Assurance Div., 2.FUJITSU Laboratories Ltd.)

https://doi.org/10.7567/SSDM.2004.A-7-1

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