[A-8-3] Gate Depletion Effect Reduction and Flat-band Voltage Control in Poly-Si/HfAlOx MOSFETs with Nanometer TaN Dots at the Top Interface

Hideaki Fujiwara, Masaru Kadoshima, Hiroyuki Ota, Hiroyuki Takaba, Nobuyuki Mise, Hideki Satake, Toshihide Nabatame, Akira Toriumi (1.MIRAI-ASET, AIST, 2.MIRAI-ASRC, AIST, 3.The Univ. of Tokyo)

https://doi.org/10.7567/SSDM.2005.A-8-3