[C-8-3] Gate Overlapped Raised Extension Structure (GORES) MOSFET by Using In-situ Doped Selective Si Epitaxy

Y. Tateshita, T. Imoto, Y. Kikuchi, J. Wang, T. Kataoka, Y. Miyanami, H. Ikeda, S. Fujita, T. Landin, C. Arena, H. Iwamoto, T. Ohno, T. Kobayashi, M. Saito, S. Kadomura, N. Nagashima (1.Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporation, 2.ASM America Inc.)

https://doi.org/10.7567/SSDM.2005.C-8-3