[C-8-4] A Double-Gate device architecture optimization for sub-45nm digital CMOS technologies using cell-based timing analysis

R. Surdeanu, G. Doornbos, R. Ng, P. Christie, V.H. Nguyen, B.J. Pawlak, J.J.G.P. Loo, M.J.H.van Dal, Y.V. Ponomarev (1.Philips Research Leuven)

https://doi.org/10.7567/SSDM.2005.C-8-4