A Memory-Based Programmable Logic Device Using a Look-Up Table Cascade with Synchronous SRAMs

Kazuyuki NAKAMURA; Tsutomu SASAO; Munehiro MATSUURA; Katsumasa TANAKA; Kenichi YOSHIZUMI; Hiroki NAKAHARA; Yukihiro IGUCHI

doi:https://doi.org/10.7567/SSDM.2005.D-6-2

2005 International Conference on Solid State Devices and Materials

2005年9月12日〜 2005年9月15日
International Conference Center Kobe, Kobe, Japan

[D-6-2] A Memory-Based Programmable Logic Device Using a Look-Up Table Cascade with Synchronous SRAMs

Kazuyuki NAKAMURA、Tsutomu SASAO、Munehiro MATSUURA、Katsumasa TANAKA、Kenichi YOSHIZUMI、Hiroki NAKAHARA、Yukihiro IGUCHI (1.Kyushu Institute of Technology、2.Meiji University)

https://doi.org/10.7567/SSDM.2005.D-6-2

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