CMOS Compatible Si-Nanowire Inverter Logic Gate for Low Power Applications

N. Singh; K.D. Buddharaju; S.C. Rustagi; Selin H.G. Teo; A. Agarwal; L.Y. Wong; L.J. Tang; C.H. Tung; J. Yu; G. Q. Lo; N. Balasubramanian; D. L. Kwong

doi:https://doi.org/10.7567/SSDM.2007.H-5-3

2007 International Conference on Solid State Devices and Materials

2007年9月18日〜 2007年9月21日
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[H-5-3] CMOS Compatible Si-Nanowire Inverter Logic Gate for Low Power Applications

N. Singh、K.D. Buddharaju、S.C. Rustagi、Selin H.G. Teo、A. Agarwal、L.Y. Wong、L.J. Tang、C.H. Tung、J. Yu、G. Q. Lo、N. Balasubramanian、D. L. Kwong (1.Institute of Microelectronics)

https://doi.org/10.7567/SSDM.2007.H-5-3

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