[P-3-3] Extra Bonus on Transistor Optimization with Stress Enhanced Notch-gate Technology for sub-90nm CMOSFET

W.-K. Yeh, C.-M. Lai, Y.-K. Fang, C.-W. Hsu, C.-T. Lin, C.-H. Hsu, L.-W. Chen, Y.-T. Huang, C.-T. Tsai (1.Department of Electrical Engineering, National University of Kaohsiung, 2.Institute of Microelectronics, National Cheng Kung University, 3.United Microelectronics Corporation, Central R&D Division)

https://doi.org/10.7567/SSDM.2007.P-3-3