Fabrication and Location of 3-nm Pt Wires onto Silicon Surfaces

M. Kobayashi; K. Onodera; Y. Watanabe; K. Shiba; I. Yamashita

doi:https://doi.org/10.7567/SSDM.2010.G-8-5

2010 International Conference on Solid State Devices and Materials

Sep 21, 2010 - Sep 24, 2010
The University of Tokyo, Tokyo, Japan

[G-8-5] Fabrication and Location of 3-nm Pt Wires onto Silicon Surfaces

M. Kobayashi^1,2, K. Onodera², Y. Watanabe³, K. Shiba¹, I. Yamashita^2,4 (1.Japanese Foundation for Cancer Res., 2.NAIST, 3.Univ. of Tokyo, 4.Panasonic Corp. , Japan)

https://doi.org/10.7567/SSDM.2010.G-8-5

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