Optimization of Urea-EnFET Based on Ta<sub>2</sub>O<sub>5</sub> Layer with Post Annealing

T. C. Yu; C. E. Lue; W. Y. Chuang; C. M. Yang; D. Pijanowska; C. S. Lai

doi:https://doi.org/10.7567/SSDM.2010.P-11-6

[P-11-6] Optimization of Urea-EnFET Based on Ta₂O₅ Layer with Post Annealing

T. C. Yu¹、C. E. Lue¹、W. Y. Chuang¹、C. M. Yang²、D. Pijanowska³、C. S. Lai¹ (1.Chang Gung Univ.、2.Device Section, Department of WAT and Devices, Inotera Memories Inc. , Taiwan、3.Institute of Biocybernetics and Biomedical Engineering, Polish Academy of Sciences , Pol)

https://doi.org/10.7567/SSDM.2010.P-11-6

2010 International Conference on Solid State Devices and Materials

[P-11-6] Optimization of Urea-EnFET Based on Ta2O5 Layer with Post Annealing

[P-11-6] Optimization of Urea-EnFET Based on Ta₂O₅ Layer with Post Annealing