Impact of Engineered Buried Ti layer on the Memory Performance of HfOx RRAM

P. S. Chen; H. Y. Lee; Y. S. Chen; P. Y. Gu; F. Chen; M. J. Tsai

doi:https://doi.org/10.7567/SSDM.2010.P-4-7

2010 International Conference on Solid State Devices and Materials

2010年9月21日〜 2010年9月24日
The University of Tokyo, Tokyo, Japan

[P-4-7] Impact of Engineered Buried Ti layer on the Memory Performance of HfOx RRAM

P. S. Chen¹、H. Y. Lee^2,3、Y. S. Chen^2,3、P. Y. Gu²、F. Chen²、M. J. Tsai² (1.MingShin University of Science & Technology、2.Indus. Tech. Res. Inst.、3.National Tsing Hua Univ. , Taiwan)

https://doi.org/10.7567/SSDM.2010.P-4-7

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