[C-5-1] Through Silicon Via (TSV) Fabrication with Low-k Dielectric Liner and Its Implications on Parasitic Capacitance and Leakage Current

L. Zhang^1,2、H. Y. Li¹、S. Gao¹、C. S. Tan² (1.A*STAR、2.Nanyang Technological University , Singapore)

https://doi.org/10.7567/SSDM.2011.C-5-1