Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultra-Low Power Logic Circuits

M. C. Sun; S. W. Kim; H. W. Kim; G. Kim; H. Kim; J.H. Lee; H. Shin; B. G. Park

doi:https://doi.org/10.7567/SSDM.2011.D-4-2

2011 International Conference on Solid State Devices and Materials

Sep 27, 2011 - Sep 30, 2011
Aichi Industry & Labor Center (WINC AICHI), Nagoya, Japan

[D-4-2] Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultra-Low Power Logic Circuits

M. C. Sun^1,2, S. W. Kim¹, H. W. Kim¹, G. Kim¹, H. Kim¹, J.H. Lee¹, H. Shin¹, B. G. Park¹ (1.Seoul National Univ., 2.Samsung Electronics Co., Ltd. , Korea)

https://doi.org/10.7567/SSDM.2011.D-4-2

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