[D-4-2] Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultra-Low Power Logic Circuits

M. C. Sun^1,2、S. W. Kim¹、H. W. Kim¹、G. Kim¹、H. Kim¹、J.H. Lee¹、H. Shin¹、B. G. Park¹ (1.Seoul National Univ.、2.Samsung Electronics Co., Ltd. , Korea)

https://doi.org/10.7567/SSDM.2011.D-4-2