Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO<sub>2</sub> VS Si-cap

J. Mitard; F. Bellenger; L. Witters; B. De Jaeger; B. Vincent; L. Nyns; K. Martens; E. Vrancken; G. Wang; D. Lin; R. Loo; M. Caymax; K. De Meyer; M. Heyns; N. Horiguchi

doi:https://doi.org/10.7567/SSDM.2011.E-1-1

2011 International Conference on Solid State Devices and Materials

Sep 27, 2011 - Sep 30, 2011
Aichi Industry & Labor Center (WINC AICHI), Nagoya, Japan

[E-1-1] Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO₂ VS Si-cap

J. Mitard¹, F. Bellenger¹, L. Witters¹, B. De Jaeger¹, B. Vincent¹, L. Nyns¹, K. Martens¹, E. Vrancken¹, G. Wang¹, D. Lin¹, R. Loo¹, M. Caymax¹, K. De Meyer¹, M. Heyns¹, N. Horiguchi¹ (1.IMEC , Belgium)

https://doi.org/10.7567/SSDM.2011.E-1-1

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2011 International Conference on Solid State Devices and Materials

[E-1-1] Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO2 VS Si-cap

[E-1-1] Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO₂ VS Si-cap