The Japan Society of Applied Physics

[F-2-2] Data Disturbance-free NAND-type Ferroelectric-gate Thin Film Transistor Array using Solution-processed ITO and Stacked (BLT/PZT) Gate Insulator

B. N. Q. Trinh1, T. Miyasako1, T. Kaneda1, P. V. Thanh2, P. T. Tue2, E. Tokumitsu1,3, T. Shimoda1,2 (1.JST, 2.JAIST, 3.Tokyo Tech , Japan)

https://doi.org/10.7567/SSDM.2011.F-2-2