[F-4-1] A Zero Additional Process to Standard CMOS, 8F², Scalable Embedded Flash Memory with Drain-side Assisted Erase Scheme

Y. Shinozuka¹, K. Miyaji¹, K. Takeuchi¹ (1.Univ. of Tokyo , Japan)

https://doi.org/10.7567/SSDM.2011.F-4-1