[P-3-9] Modeling Subthreshold Current and Threshold Voltage of Fully-Depleted Double-gate Junctionless(J-less) Transistors

Z. M. Lin¹, H. C. Lin^1,2, K. M. Liu³, T. Y. Huang¹ (1.National Chiao Tung Univ., 2.Labs of National Nano Device, 3.National Dong Hwa Univ. , Taiwan)

https://doi.org/10.7567/SSDM.2011.P-3-9