[PS-5-15] Impact on delay due to random telegraph noise under low voltage operation in logic circuits

S. Nishimura¹, T. Matsumoto¹, K. Kobayashi^2,3, H. Onodera^1,3 (1.Kyoto Univ., 2.Kyoto Inst. Tech., 3.JST CREST , Japan)

https://doi.org/10.7567/SSDM.2012.PS-5-15