Physical Limitation of pn Junction in Two Dimensional Si Layers for Future CMOS

T. Mizuno; Y. Nakahara; Y. Nagata; Y. Suzuki; Y. Kubodera; Y. Shimizu; T. Aoki; T. Sameshima

doi:https://doi.org/10.7567/SSDM.2013.D-1-2

2013 International Conference on Solid State Devices and Materials

Sep 24, 2013 - Sep 27, 2013
Hilton Fukuoka Sea Hawk, Fukuoka, Japan

[D-1-2] Physical Limitation of pn Junction in Two Dimensional Si Layers for Future CMOS

T. Mizuno¹, Y. Nakahara¹, Y. Nagata¹, Y. Suzuki¹, Y. Kubodera¹, Y. Shimizu¹, T. Aoki¹, T. Sameshima² (1.Kanagawa Univ., 2.Tokyo Univ. of Agriculture/Tech. (Japan))

https://doi.org/10.7567/SSDM.2013.D-1-2

▲