[M-6-2] Spin-transistor characteristics of pseudo-spin-MOSFETs monolithically-integrated by utilizing a multi-project-wafer CMOS chip

R. Nakane^1,5, Y. Shuto^2,3,5, H. Sukegawa^4,5, Z.C. Wen^4,5, S. Yamamoto^2,5, S. Mitani^4,5, M. Tanaka^1,5, K. Inomata^4,5, S. Sugahara^2,5 (1.Univ. of Tokyo, 2.Tokyo Institute of Technology, 3.Kanagawa Academy of Science and Technology, 4.National Institute for Materials Science, 5.CREST, Japan Science and Technology Agency (Japan))

https://doi.org/10.7567/SSDM.2013.M-6-2