[M-7-3] Wide Operational Margin Capability of 1kbit STT-MRAM Array Chip with 1-PMOS and 1-Bottom-Pin-MTJ Type Cell

H. Koike¹, T. Ohsawa¹, S. Miura², H. Honjo², S. Ikeda¹, T. Hanyu¹, H. Ohno¹, T. Endoh¹ (1.Tohoku Univ., 2.NEC Corp. (Japan))

https://doi.org/10.7567/SSDM.2013.M-7-3