The Japan Society of Applied Physics

[M-7-3] Wide Operational Margin Capability of 1kbit STT-MRAM Array Chip with 1-PMOS and 1-Bottom-Pin-MTJ Type Cell

H. Koike1, T. Ohsawa1, S. Miura2, H. Honjo2, S. Ikeda1, T. Hanyu1, H. Ohno1, T. Endoh1 (1.Tohoku Univ., 2.NEC Corp. (Japan))

https://doi.org/10.7567/SSDM.2013.M-7-3