Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications

R. Nebashi; Y. Tsuji; H. Honjo; N. Sakimura; A. Morioka; K. Tokutome; S. Miura; S. Fukami; M. Yamanouchi; K. Kinoshita; T. Hanyu; T. Endoh; N. Kasai; H. Ohno; T. Sugibayashi

doi:https://doi.org/10.7567/SSDM.2013.M-8-3

[M-8-3] Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications

R. Nebashi¹, Y. Tsuji¹, H. Honjo¹, N. Sakimura^1,2, A. Morioka¹, K. Tokutome¹, S. Miura¹, S. Fukami², M. Yamanouchi², K. Kinoshita², T. Hanyu², T. Endoh², N. Kasai², H. Ohno², T. Sugibayashi¹ (1.NEC Corp., 2.Tohoku Univ. (Japan))

https://doi.org/10.7567/SSDM.2013.M-8-3

2013 International Conference on Solid State Devices and Materials

[M-8-3] Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications