[PS-2-5] Self-Assembly and Electrostatic(SAE)Carrier Technology for Via-Last Backside-Via Multichip-to-Wafer 3D Integration

H. Hashiguchi¹, T. Fukushima¹, J.C. Bea¹, K.W. Lee¹, T. Tanaka¹, M. Koyanagi¹ (1.Tohoku Univ. (Japan))

https://doi.org/10.7567/SSDM.2013.PS-2-5