[PS-5-3] A Stabilization Technique for Intermediate Power Level in Stacked-Vdd ICs using Parallel I/O Signal Coding
T. Nishiyama1, T. Koizuka1, H. Okamura1, T. Yamanokuchi1, K. Nakamura1
(1.Kyushu Inst. of Tech. (Japan))
https://doi.org/10.7567/SSDM.2013.PS-5-3
