[A-7-1] A Power-gated 32bit MPU with a Power Controller Circuit Activated by Deep-sleep-mode Instruction Achieving Ultra-low Power Operation

H. Koike¹、T. Ohsawa¹、S. Miura¹、H. Honjo¹、K. Kinoshita²、S. Ikeda¹、T. Hanyu¹、H. Ohno¹、T. Endoh¹ (1.Tohoku Univ.、2.NEC Corp. (Japan))

https://doi.org/10.7567/SSDM.2014.A-7-1