[J-1-5] Design Guidelines of Steep Subthreshold TFET to Minimize Energy of Logic Circuits

H. Fuketa¹, K. Yoshioka¹, K. Fukuda², T. Mori², H. Ota², M. Takamiya¹, T. Sakurai¹ (1.Univ. of Tokyo, 2.AIST (Japan))

https://doi.org/10.7567/SSDM.2014.J-1-5