9:30 AM - 9:50 AM

[E-6-2] Evaluation of 2-D Local Stress Distribution in Stacked IC Chip Using Stress-Induced Retention Time Modulation of DRAM Cell Array

^○S. Tanikawa¹, H. Hashiguchi¹, Y. Sugawara¹, H. Kino¹, T. Fukushima¹, M. Koyanagi¹, T. Tanaka¹ (1.Tohoku Univ.(Japan))

https://doi.org/10.7567/SSDM.2015.E-6-2