39% tAC Improvement, 11% Energy Reduction, 32Kbit 1R/1W 2port SRAM using Two-stage Read Boost and Write-Boost after Read Sensing Scheme

Y. Yamamoto

doi:https://doi.org/10.7567/SSDM.2015.F-6-1

9:00 AM - 9:20 AM

[F-6-1] 39% tAC Improvement, 11% Energy Reduction, 32Kbit 1R/1W 2port SRAM using Two-stage Read Boost and Write-Boost after Read Sensing Scheme

^○Y. Yamamoto¹, S. Moriwaki¹, A. Kawasumi², S. Miyano³, H. Shinohara⁴ (1.Socionext Inc., 2.Toshiba Corp., 3.Previously with STARC, 4.Waseda Univ.(Japan))

https://doi.org/10.7567/SSDM.2015.F-6-1

2015 International Conference on Solid State Devices and Materials

[F-6-1] 39% tAC Improvement, 11% Energy Reduction, 32Kbit 1R/1W 2port SRAM using Two-stage Read Boost and Write-Boost after Read Sensing Scheme