Stacked-Nanowire and FinFET Transistors: Guidelines for the 7nm Node

L. Gaben

doi:https://doi.org/10.7567/SSDM.2015.K-4-2

16:10 〜 16:30

[K-4-2] Stacked-Nanowire and FinFET Transistors: Guidelines for the 7nm Node

^○L. Gaben¹, S. Barraud², M. A. Jaud², S. Martinie², O. Rozeau², J. Lacord², G. Hiblot¹, S. Monfray¹, F. Boeuf¹, T. Skotnicki¹, F. Balestra³, M. Vinet² (1.STMicroelectronics, 2.CEA-LETI, 3.IMEP-LAHC(France))

https://doi.org/10.7567/SSDM.2015.K-4-2

2015 International Conference on Solid State Devices and Materials

[K-4-2] Stacked-Nanowire and FinFET Transistors: Guidelines for the 7nm Node