[PS-3-10] Impacts of Threshold Voltage Design for Monolithic 3D 6T SRAM with Si and InGaAs-n/Ge-p Devices considering Interlayer Coupling

^○K. C. Yu¹, C. H. Yu¹, V. P. H. Hu¹, P. Su¹, C. T. Chuang¹ (1.National Chiao Tung Univ.(Taiwan))

https://doi.org/10.7567/SSDM.2015.PS-3-10