[PS-6-25L] Design of Drain for Low off Current in GaAsSb/InGaAs Tunnel FETs

^○S. Iwata¹, W. Lin¹, K. Fukuda^1,2, Y. Miyamoto¹ (1.Tokyo Tech, 2.AIST(Japan))

https://doi.org/10.7567/SSDM.2015.PS-6-25L