The bit density of NAND flash memory has faithfully followed Moore’s law, starting from 4 Mb in 1991 to 128 Gb over the past 25 years since the first introduction of NAND flash memory in 1987. The conventional floating-gate cell has proved its excellent cell performance and reliability than other alternative types of cell. Consequently it has scaled down to 1ynm node successfully. In the planar NAND flash memory technology, the cell-to-cell coupling, program disturbance and data retention as well as the process complexity and the photo-lithography limitation have been recognized as the most critical scaling barriers. Various materials, structures, operation algorithms were adopted to overcome these barriers. To surmount the technical hurdles of the planar NAND Flash device, the 3D vertical NAND structures of BICS based on the SONOS cell in 2007, TCAT based on TANOS - CTF cell (charge trap flash) in 2009, and Floating-Gate Vertical NAND in 2015 have been developed, respectively. In this course, major technical issues and the solutions of the planar NAND Flash devices will be addressed. Moreover, the key features and structures of 3D Vertical NAND will be reviewed.