The cache memory area in CPU and SoC chips is increasing since the performance can be effectively improved by increasing the embedded cache memory capacity. A high performance CPU has a cache memory of over 20-30 MB. These chips are occupied almost entirely by the cache memory and their power consumption is determined mainly by the cache memory.
One way to avoid both the increased cache memory area and increased power consumption by the cache memory is to use spin-transfer torque magnetic RAMs (STT-MRAMs). Cache memories require high density, no limitations in the number of read and write cycles, high speed reading and writing, and lack of leakage. I think STT-MRAMs are the only potential solution.
This short course reviews a current status of the development of STT-MRAMs and their integration with the back-end-of-line (BEOL) process to replace conventional embedded SRAM cache memories.