Enhancement of Capacitance Benefit by Drain Offset Structure in TFET Circuit Speed Associated with Tunneling Probability Increase

2017 International Conference on Solid State Devices and Materials

Sep 19, 2017 - Sep 22, 2017
Sendai International Center

11:45 AM - 11:47 AM

^○H. Asai¹, T. Mori¹, T. Matsukawa¹, J. Hattori¹, K. Endo¹, K. Fukuda¹ (1.AIST (Japan))