12:01 〜 12:03
[PS-3-14 (Late News)] TCAD simulation of planar single-gate Si tunnel FET with average subthreshold swing less than 60 mV/dec for 0.3 V operation
○K. Kukita1, T. Uechi1, J. Shimokawa1, M. Goto1, Y. Yokota1, S. Kawanaka1, T. Tanamoto2, M. Koyama2, H. Tanimoto1, S. Takagi3
(1.Toshiba Memory Corp. (Japan), 2.Toshiba Corp. (Japan), 3.Univ. of Tokyo (Japan))