Traditional CMOS scaling has confronted a variety of difficulties, attributed to essential Si material properties as well as practical problems such as limitation of lithography, performance variation, cost and so on. Here, reduction in both device foot print and power consumption is the most serious concerns for realizing future integrated systems. Ultrathin body channels and multi-gate structures, resulting in FinFETs and nanowire MOSFETs, are indispensable in order to minimize short channel effects and to decrease the device size. On the other hand, the reduction in power consumption requires the decrease in supply voltage, which can be realized by two strategies. One is the increase in on-current due to higher mobility (velocity) channel materials with low effective mass. The other is the development of steep slope devices with lower sub-threshold swing than CMOS. From these points of view, this short course will deliver the current status and future prospects of these advanced MOS device technologies for 5-nm technology node and beyond with an emphasis on non-conventional materials and device structures for low power applications. The content can include typical examples of advanced CMOS, SiGe/Ge/III-V CMOS and steep slope devices such as tunneling FETs and negative capacitance gate MOSFETs.